Optimization of silicon technology for the IBM System z9
نویسندگان
چکیده
technology for the IBM System z9 D. J. Poindexter S. R. Stiffler P. T. Wu P. D. Agnello T. Ivers S. Narasimha T. B. Faure J. H. Rankin D. A. Grosch M. D. Knox D. C. Edelstein M. Khare G. B. Bronner H.-J. Nam S. A. Butt IBM 90-nm silicon-on-insulator (SOI) technology was used for the key chips in the System z9e processor chipset. Along with system design, optimization of some critical features of this technology enabled the z9e to achieve double the system performance of the previous generation. These technology improvements included logic and SRAM FET optimization, mask fabrication, lithography and wafer processing, and interconnect technology. Reliability improvements such as SRAM optimization and burn-in reliability screen are also described.
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ورودعنوان ژورنال:
- IBM Journal of Research and Development
دوره 51 شماره
صفحات -
تاریخ انتشار 2007